The Electro-Static Discharge (ESD) problem is one of the first causes of redesign, after initial design and fabrication (e.g., ‘first silicon’), for integrated circuits. A wide range of ESD solutions already exists but they are dedicated to protect only one kind of circuit. Hence, different ESD structures have to be developed for each application. In consequence, the ESD protection structures must be redefined and redeveloped for each technology and application.
Another point which has to be considered is the current absorption during the non-operating mode of the protection system.
An effective ESD protection has to be able to support ESD-HBM (Human Body Model minimum 2KV) and -MM (Machine Model minimum 200V) stresses with a minimum current consumption in normal operating mode. These protection structures also have to be able to support and to evacuate a minimum current of 1.33 A during ESD/HBM pulse. These structures must be efficient throughout the whole system lifetime.
It is known, for example from the publication by James W. Miller, Michael G. Khazhinsky and James C. Weldon titled “Engineering the cascoded NMOS output buffer for maximum Vt1” EOS-ESD, Symposium Proceeding 2000, to increase protection threshold voltage (Vt1) by replacing a single output buffer NMOSFET with 2 series or cascoded NMOSFETs. Such a Vt1 engineered output buffer offers advantage in ESD robustness, cost and process portability. However, Vt1 is sensitive to spacing between upper collector and lower emitter in MOS integrated circuit structure, and under the output NMOSFET lies a parasitic LNPN bipolar transistor. This LNPN transistor may turn on and undesirably provide an alternate ESD path.
From the publication by V. De Hey, G. Groeseneken, B. Keppens, M. Natarajan, Vacaresse and G Gallopyn titled “Design and analysis of new protection structures for smart Power Technology with controlled trigger and holding voltage”, IEEE Physics symposium, Orlando, Fla., 2001, there is known an ESD protection structure based on bipolar transistors. The trigger and holding voltage can be adjusted. By adjusting the lateral base width, the bipolar conduction path (vertical or lateral) can be selected. The voltage range of this structure is not sufficient to cover all the product needs. Two bipolar transistors have to be controlled in order to have to the best distribution of constrained energy.
From patent publication EP 1 162 664 A1 there is known a low on-resistance lateral semiconductor device, such as a LDMOS (laterally diffused MOS transistor), comprising a drift region having a first surface and a first conductivity type, first and second semiconductor regions extending into the drift region from the first surface, and an additional region having a second conductivity type between the first and second semiconductor regions. The additional region extends into the drift region from the first surface and forms a junction dividing the electric field between the first and second semiconductor regions when a current path is established between the first and second semiconductor regions. This allows the doping concentration of the drift region to be increased, thereby lowering the on-resistance of the device. This device provides good distribution of the electric field, but ESD protection structures are not addressed (only lateral power MOS transistor are addressed in the publication).
However, existing ESD protection structures are based on different approaches to provide a scalable voltage in ESD structures. Bipolar transistors assembled in cascade are one of the solutions but these structures exhibit an important leakage current. For example, ESD protection structures are known based on the principal of Zener diodes located between gate and drain and between gate and source, the number of diodes allowing the snapback voltage level to be determined.
A physical study of the parasitic phenomenon in NMOS structure and their utilization as ESD protection in CMOS technology allows a better understanding of the parasitic operating mode (parasitic bipolar transistor) and their control, but control in such a study is most readily realized by addition of external passive elements like resistance between Gate/Source and capacitance between Drain/Gate. An important difficulty in implementing findings of such a study is in the choice of internal protection structures.
A need therefore exists for SPS (Scalable Protection Structures) wherein the abovementioned disadvantage(s) may be alleviated.